PCI Express發(fā)展速度相對(duì)變緩的時(shí)候,Synopsys正式推出一款PCI Express 2.0版IP芯片,聲稱5GHz技術(shù)將獲得設(shè)計(jì)人員的廣泛關(guān)注。
Synopsys此后將供應(yīng)用于Express 2.0版物理層、控制器和驗(yàn)證的IP。
“其它公司也可能將提供一項(xiàng)或兩項(xiàng)IP,但是做不到我們的高度”,Synopsys混合信號(hào)IP主管Navraj Nandra表示,“當(dāng)你(設(shè)計(jì)人員)必須和兩家或多家IP供應(yīng)商打交道時(shí),事情復(fù)雜會(huì)要復(fù)雜得多。”
新的IP支持4路和8路Express通道,Synopsys認(rèn)為這是最常見的配置。然而,至少有一家交換器制造商正在生產(chǎn)一款采用多個(gè)IP核的32通道Express交換器芯片。
Synopsys所推出的IP包括嵌入式診斷和ATE測(cè)試向量,此外也可通過數(shù)字測(cè)試器完成測(cè)試模擬信號(hào)的功能,這要?dú)w功于Synopsys通過收購初創(chuàng)公司Accelerant Networks所獲得的技術(shù)。
此次所推出的IP核目前優(yōu)化用于TSMC的65nm 2V工藝和包括Chartered, IBM和三星在內(nèi)的制造同盟。在今年底前將會(huì)推出面向40nm TSMC工藝的版本草案。
“似乎大多數(shù)晶圓廠都趨向于采用40nm []工藝”,Nandra表示,“采用40和45nm工藝所生產(chǎn)的IP芯片不同之處在于兩者價(jià)格相同但體積縮小19%。
翻頁查看英文原文:
Synopsys debuts 5 GHz PCI express core
Synopsys officially rolls out a silicon core for PCI Express 2.0 Monday (April 28), claiming the 5 GHz technology is beginning to get attention from designers. The news comes at a time when experts say the industry is moving at a relatively slow pace down the Express road map.
Synopsys is supplying silicon intellectual property for the physical layer, controller and verification portions of the Express 2.0 spec.
"Other companies tend to have one or two of the components but not all three," said Navraj Nandra, director of mixed-signal IP at Synopsys. "When you have to work with more than one silicon IP vendor, it gets complicated," he said.
The IP comes in versions supporting four and eight lanes of Express, which Synopsys believes are the most common configurations. However, at least one switch maker is creating a 32-lane Express switch chip using multiple copies of the core.
The IP includes embedded diagnostics and ATE test vectors. It also supports an ability to test analog functions via a digital tester, thanks to technology Synopsys acquired with startup Accelerant Networks.
The cores currently are optimized for 2V operation in the 65nm process technology of TSMC and the Common Platform group which includes Chartered, IBM and Samsung. A version drawing for a 40nm TSMC process will be available before the end of the year.
"It looks like most fabs are going after 40nm [and operation] aggressively," said Nandra."The difference between 40 and 45nm comes down to a 19 percent savings in area for the same price," he added.
