發布日期：2022-07-14 點擊率：79
今年1月,Roelandts從他擔任的賽靈思公司總裁兼首席執行官的角色上升職,成為公司董事會主席。他1996年被任命為公司總裁兼首席執行官,把公司從年銷售額5.6億美元發展成為2007財年的18億美元。
目前,公司已經任命Moshe Gavrielov擔任總裁兼首席執行官。Gavrielov曾任以色列Verisity有限公司的首席執行官,該公司最終在2005年由Cadence公司兼并。Gavrielov已經在最近表示,他打算在他的任期內把賽靈思發展成為年銷售收入100億美元的公司。
EE Times:PLD行業的弱點是什么？
Wim Roelandts: 常見的可編程邏輯芯片比較大且更為昂貴,而這就是為什么我們持續地推動摩爾定律,它對我們管用,但是,對于大多數行業它已經不管用。
如果你設計一款調制解調器芯片,那么,沒有必要把它縮小至45納米。需要采用先進工藝技術的應用越來越少,這些工藝技術僅僅被那些需要非常大量的晶體管的人所使用。那就是為什么在某些應用,像汽車行業,仍然采用180納米和130納米工藝技術。甚至大多數消費電子設備并不是采用先進的工藝技術,而是180納米、130納米以及90納米工藝技術。
在過去的幾年中,可編程邏輯已經讓我們繼續利用摩爾定律,并繼續驅動成本的降低,因此,摩爾定律開始在更多的應用中被采用,如消費電子應用中,舉例來說,像平板電視機、蜂窩電話以及機頂盒等等。汽車是另一個好例子,其中,越來越多的可編程器件被采用,因為可編程性的成本正變得越來越低,這要歸功于摩爾定律。因此,在可編程邏輯器件行業,靈活性依然是優點,缺點就是需要不斷的超越摩爾定律。
可編程邏輯器件的另一個缺點就是,如果你構建一塊較大規模的芯片,那么,你就需要采用大量的軟件、應用軟件、IP以及諸如此類的模塊,從而使設計更為復雜。過去,FPGA公司提供一顆芯片和一套編譯器,客戶完成一切工作。現在,他們希望獲得更多的IP,這就改變了FPGA公司的運營方式。我們在幾年以前就認識到這一點,因此,我們建立了強大的組織來為各個客戶開發IP以及對IP進行集成。
EE Times:對于當今的PLD行業來說,在哪里的機會最大？
WR: 最大的機會就是讓PLD被應用于大批量的市場。當我開始為賽靈思工作,也就是12年半以前,每年6萬片對我們來說就是大批量了。現在,對單一型號的產品,我們每年最大的批量是8百萬片,并且它被用于平板電視系統。在未來的幾年中,我們將進入更為大批量的市場,特別是高端產品市場,而隨著時間的推移,我們將覆蓋低端大批量產品市場。
第二個機會就是提供更為集成的解決方案。現代的FPGA不再僅僅是可編程邏輯,而是介于ASIC和FPGA之間的混合芯片,它包含微處理器、收發器以及許多其它單元。我們采用非常先進的技術來構建芯片。在可編程邏輯芯片中加入少量硬核的確不會大幅增加芯片的尺寸,但是,它極大地提升了價值。
通過把諸如存儲器和DSP核這樣的單元集成在芯片上,我們提高了價值。賽靈思一直在把越來越多的硬核加入FPGA之中,因為它改進性能、提高速度且降低功耗。
ASSP與FPGA的比較
EE Times:在FPGA領域出現了向著低成本發展的趨勢,從而造成市場上自相殘殺的現象,您對此怎么看？
WR: 我認為那不是威脅,但是,更確切地說,那是行業的標準。每兩年就有采用先進技術的產品上市,它們的成本更低。存儲器的容量一年增加40%,而邏輯單元的數量一年增加大約70%。
在過去的幾年中,在邏輯單元的消耗和價格的下降之間沒有太多的差異,因此,該行業的增長率不是非常大,大約每年為10%。在進一步降低價格和建立新應用之間一直存在持續的戰爭。這是好事情,因為當價格快速下降時,我們能夠捕獲新的市場,否則的話,就不可能做到這一點。
EE Times:您認為ASSP和FPGA相比怎么樣？
WR: ASSP就是ASIC的終極版。現在,被設計的ASIC越來越少,因為所涉及的成本高所致。ASIC可以由ASSP或PLD所取代。目前,ASSP已經取得了非常大的成功,但是,最終它們的確定跟ASIC是一樣的。ASSP被提供給4-5個客戶,這樣看來,ASIC變得經濟是沒有理由的,隨著時間的推移,ASSP也將發生相同的事情。
越來越多的公司正在向大批量ASSP轉移,因為人們發現投資較小批量的產品從經濟角度來說是沒有理由的。隨著時間的推移,ASSP將必須把重點放在較大批量的應用上,與此同時,較小批量的應用將由PLD所主宰,因為采用PLD更為經濟。
EE Times:您今年的策略是什么？
WR: 我們打算從軟件、IP以及其它方面考慮提供更為完整的解決方案。ASSP供應商提供芯片和軟件并告訴客戶“你把它放在板上就工作了”。為了讓FPGA抓住那個市場,我們必須提供不僅僅是FPGA,而且有比ASSP中硬核工作更快的軟IP,并且我們將確保它在一塊均能工作。這一策略將最終引領我們成為一個100億美元的公司,然而,這可能要花上10年。
EE Times:你們的競爭對手Altera今年將向40納米轉移,從這方面說,你們有什么計劃？
WR: 我們正在設計40納米的產品。作為主席,我們無法就產品開發計劃和付運時間做出承諾,但是,我能夠說的就是,在2006年推出了65納米的產品,并且每兩年我們將推出新一代的產品,因此,我把它留給你自己做出結論。
EE Times:您在兼并方面采取什么策略？
WR: 我們出于技術原因考慮會兼并一家公司,而不是為了攫取市場份額。我們分析我們的產品組合以及我們薄弱的領域所在,或者說,我們缺失的產品所在,然后,我們出手兼并一家公司。
EE Times:您如何看待公司現在的財務前景？
WR: 3月份結束的財年與去年同期持平。在2006年,我們上半年增長強勁,而下半年增長非常慢。然而,我們把去年12個季度與前年的同期進行了比較,我們的增長率為8%。我認為幾年將是比較好的年景。
我們已經處于非常強大的地位,因為我們正在市場上主推65納米產品,而在高端市場,我們的確沒有競爭對手。
翻頁查看英文原文:
Executive Interview: Xilinx chairman Wim Roelandts
Moore's Law is still valid but it does not work for most sectors of the industry today, according to Wim Roelandts, chairman of programmable logic device vendor Xilinx Inc. (San Jose, Calif.). Roelandts met EE Times Europe during his first visit to Israel, where he attented the recent Global Semiconductor Association conference.
In January, Roelandts stepped up from his post as president and CEO of Xilinx, to become the company's chairman of the board. Roelandts was named president and CEO in 1996 and grew the company's sales from $560 million to over $1.8 billion in fiscal year 2007.
The company has appointed Moshe Gavrielov president and CEO. Gavrielov was the CEO of Israel-based Verisity Ltd., which was ultimately acquired by Cadence in 2005. Gavrielov has recently stated that he intends to grow Xilinx to a $10 billion revenue company during his tenure.
EE Times : What are the weaknesses of the PLD industry?
Wim Roelandts: The usual programmable logic chips are bigger and more expensive, and this is why we continue to push Moore's law, which works for us, but does not work anymore for most industries.
If you do a modem chip there is no need to shrink it to 45 nanometers. There are fewer and fewer applications that require advanced [process] technologies. These technologies are only used by people who need very large number of transistors. That is why certain applications like automotive are still using 180-nm and 130-nm. Even most consumer devices are not using advanced [process] technologies, but rather 180-nm, 130-nm or maybe 90-nm.
In the last couple of years, programmable logic has allowed us to keep using Moore's Law, and continue to drive costs down, and therefore become used in more applications, such as consumer applications " flat panel TVs, cellphones, set-top boxes, you name it. Automotive is another good example of where more and more programmable devices are used, because the cost of programmability is becoming smaller, thanks to Moore's Law. Therefore, in PLDs the flexibility is still there as an advantage and the disadvantages are outweighed by our use of Moore's Law.
Another weakness of the PLDs is the fact that if you build bigger chips you need a lot more software, applications, IP and so on, which make things more complicated. In the past, FPGA companies supplied a chip and a compiler and the customers did everything by themselves. Now, they expect to get more IP, and this changed the way that FPGA companies operate. We saw this several years ago, and therefore we have a strong organization that develops IP for the customers and does the integration of IP.
EE Times : What are the big opportunities for the PLD industry today?
WR: The big opportunity is to have PLDs used in high volume markets. When I started working for Xilinx, twelve and a half years ago, big volume for us was maybe 60,000 units per year. Today our biggest volume is 8 millions units per year for a single socket, and it is used for a flat panel TV system. Over the years, we will be approaching even higher volume markets, especially in high end products, but with time we will reach low end products with high volume.
The second opportunity is to provide a more integrated solution. A modern FPGA is no longer just programmable logic, but rather a hybrid between an ASIC and an FPGA. It contains processors, transceivers and many other elements. We build the chip in a very advanced technology. Adding a few hard cores to that chip really does not increase the size very much, but it significantly increases the value.
By putting elements such as memories and DSP cores on chips, we increase the value. Xilinx has been adding more and more hard cores into its FPGAs, because it improves the performance and the speed and reduces power consumption.
ASSPs vs FPGAs
EE Times : There is a trend towards low cost FPGAs, causing some cannibalization of the market. Can you refer to that?
WR:I don't consider that as a threat, but more a standard of the industry. Every two years there is a new generation of products in advanced technologies, which cost less. Memory bits grow at about 40 percent a year, while logic cells grow at about 70 percent a year.
In the last couple of years there has not been much difference between the consumption of logic cells and the decline in prices, so the growth rate in the industry has not been very great — about 10 percent per year. There is a continuing battle to lower prices and get new applications. It is an advantage, because when prices go down so quickly, we can capture new markets that otherwise would not have been possible.
EE Times : How do you regard ASSPs as against FPGAs?
WR: ASSPs are the ultimate of the ASICs. Fewer ASICs are designed, because of the costs involved. ASICs can be replaced by an ASSP or a PLD. For the moment, ASSPs have been very successful, but ultimately their drawback is the same as that of an ASIC. An ASSP goes to 4 or 5 customers, so if ASICs become economically not justifiable, the same will happen with ASSPs over time.
More companies are moving to the high volume ASSPs, since people don't find it economically justifiable to invest in smaller volumes. With time, ASSPs will have to focus on the higher volume sockets, while lower volume sockets will be dominated by PLDs, because of economics.
EE Times : What is your strategy for this year?
WR : We intend to provide more complete solutions in terms of software, IP and so on. ASSP vendors provide a chip and software and tell the customer 'you put it on a board and it works'. For FPGAs to capture that segment, we have to provide not just the FPGA but also the soft IP that works much faster than the hard IP in ASSPs, and we'll make sure that it all works together. This strategy will eventually lead us to be a $10 billion company, maybe in 10 years.
EE Times : Your colleagues at Altera will be moving to 40-nm this year. What about your plans in this regard?
WR : We are designing for products in 40-nm. As chairman I cannot give commitments regarding products and shipping, but what I can say is that the 65-nm products were introduced in 2006, and every two years we come out with new generation of products, so I'll leave it to you to make your own conclusions.
EE Times : What is your strategy regarding acquisitions?
WR: We are acquiring companies for technology reasons, not in order to get market share. We look at our portfolio and where we have areas we are weak in, or that we are missing, then we go out and acquire companies.
EE Times : How do you see you financial prospects now?
WR: The fiscal year that ended in March will be about flat compared to the year before. In 2006 we had a very strong first half and a very weak second half. But when we compare our last December quarter to the same quarter a year before, we grew at 8 percent. I think this year will be better.
We are in a very strong position, because we are putting 65-nm products on the market, and in the high end we really have no competition.
